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Cmos integrated circuits

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This laboratory work intends to study the static and dynamical characteristics the CMOS integrated circuits and special features in the use of CMOS circuits.


2.1. CMOS Inverter

In the figure 5.1 is presented a pair of MOS transistors, one channel n and one channel p, which represents a CMOS inverter. This is the fundamental element on which logic gates are realized and any other functions needed in CMOS circuit design.

When a positive direct voltage (+VDD) representing logic “1”, is applied on common gates terminal, the NMOS transistor Mn opens and the PMOS transistor, Mp will be blocked. That ends with the output at the low voltage (VSS) source, “0” logic.

In the same way, if a low voltage is applied on the common gate, the PMOS transistor (Mp ) will be blocked and the NMOS transistor(Mn) will be opened. In this case, the output voltage will be at a high voltage (+VDD), which is logic “1”.

The transfer characteristic of the circuit is shown in the figure 5.2. This characteristic is dependent of the power supply voltage VDD. This characteristic can be divided in five distinct regions in which the functioning of the transistors Mn and Mp is presented in the table 5.1. VTN is the threshold voltage of the NMOS transistor (Mn), and VTP the threshold voltage of the PMOS transistor (Mp).

If the supply voltage VDD is smaller than VDDmin=VTN+│VTP│, the inverter will present a transfer characteristic with hysteresis, as shown in the figure 5.3 and the circuit cannot be used as a logic gate.

The typical value of threshold voltage on standard CMOS structures is:

hence VDDmin=3V, the minimal value of supply voltage for CMOS.

Input and output logic levels:

- V0Hmin=VDD-0.5V (typical value: VDD - 0.01V)

- V0Lmax=0.05V (typical: 0.01V)

- VIHmin=70%VDD

- VILmax=30%VDD

Noise margins:

MZL = VILmax - VOLmax=30%VDD

MZH = VIHmin - VOHmin=30%VDD

In use, the noise immunity is about 45.50% of the supply voltage.


3.1. The study of the CMOS logic gates, with the CMOS inverter presented in figure 5.1. Draw the transfer characteristic, determine the power consumption, and determine the states of the two transistors if at the input is applied a linear signal between 0V and VDD. Determine logical levels between the two states and the threshold voltage for different supply voltages. The circuit behavior will be tested if the supply voltage is under 3V by drawing the static characteristic. Examine the influence of the output load upon logical states of the circuit. For this the load resistance RS, needs first to be connected to the ground, then measure V0H, and then RS needs to be connected at VDD, and measure V0L. In the same time there can be measured the conduction resistance of the transistors Mn and Mp. Measure the noise level margins and compare them with the granted levels at different values of the supply voltage.

3.2. Analyzing the circuit in dynamic regime. Apply at the input impulses with amplitude equal with VDD and record the output, measuring the commutation times without load, and for CS=0,5nF. Examine how power consumption and commutation times are influenced by supply voltage. Also see how working frequency influence the power consumption.


    1. Short description of the CMOS inverter gate.

    2. Schemes of the circuits, tables and calculated values with the graphics of the given characteristics.

    3. Graphics obtained from the study of the dynamic regime of CMOS circuit.

    4. Observations on the nature of the differences between theoretical values and the simulated values.

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